1. Field of the Invention
The present invention relates to a memory test circuit capable of efficiently and easily executing a memory test operation for a plurality of memory circuits having different operation timings and accessing methods incorporated in a system such as a semiconductor processing device, and, more particularly, to a memory test circuit mounted on a no semiconductor processing device realizing easy memory test operation for a plurality of memory circuits having different operation timings that are executed by using different access commands.
2. Description of the Related Art
FIG. 1 is a block diagram showing a system configuration of a conventional semiconductor processing device on which two kinds of memory circuits are mounted. The memory circuits have different operation timings and operate based on different access commands.
In FIG. 1, the reference number 101 designates a first memory circuit whose memory size is 1 MB, and 102 denotes a second memory circuit whose memory size is 1 MB. Those memory circuits 101 and 102 are different in type. For example, the memory circuits 101 and 102 use different access commands and have different operation timings. The reference number 100 indicates a system as a conventional semiconductor processing device on which the first memory circuit 101 and the second memory circuit 102 are mounted. Each of the first memory circuit 101 and the second memory circuit 102 is a Dynamic Random Access Memory (DRAM).
The first memory circuit 101 and the second memory circuit 102 input address signals indicating addresses ADDRESS 3 and 4, access commands 3 and 4 as control signals, and other control signals R/W 3 and 4 to be used for controlling data read/write access operation, and then outputs data items DATA 3 and DATA 4 according to the above addresses and the control signals, respectively.
FIG. 2 is a timing chart showing the timing of a data read operation in the first memory 101. In FIG. 2, the reference character PHIA designates a clock signal to be used for the operation of the first memory 101, and A2HCAADDR denotes an address signal such as a row address and a column address. The reference character A1HCDDE indicates a control signal that indicates a timing to output data read from the first memory circuit 101 to data bus (not shown). The reference characters A1LCRAS and A1LCCAS designate a RAS signal and a CAS signal for the first memory 101, respectively.
The reference character A1LCWE designates a control signal indicating a data write to the memory when its level is a Low level (L level), and a data read from the memory when its level is a High level (H level).
FIG. 2 shows a case of the data read because the control signal A1LCWE is the H level. The reference character N1INDATA designates data on the data bus that is read out from the first memory circuit 101 as a DRAM.
The second memory circuit 102 operates based on a clock signal CLK of 25 MHz and it is different in operation timing from the first memory circuit 101 that operates based on a clock signal of 100 MHz.
FIG. 3 is a timing chart showing the timing of the data read operation in the second memory circuit 102. In the timing chart shown in FIG. 3, the reference character CLK designates a clock signal, A  less than   greater than  denotes an address signal such as a row address and a column address. The reference character OE designates a control signal indicating an output timing of data read from the second memory circuit 102, and /WE denotes a control signal indicating a writing timing of data to the second memory circuit 102. The reference character D  less than   greater than  designates data read from the second memory circuit 102 as a DRAM.
Next, a description will be given of the operation of the conventional semiconductor processing device.
In the memory test of the semiconductor processing device on which two kinds of memory circuits 101 and 102 are mounted shown in FIG. 1, the first memory circuit 101 and the second memory circuit 102 are executed in different timings by using different access commands, respectively.
First, the memory test for the first memory circuit 101 is executed by the following manner.
In the data read operation, the row address A2HCAADDR and the RAS signal A1LCRAS and the like are outputted to the first memory circuit 101 at the timing T42 in order to set the first memory circuit 101 in an active state.
Next, at the timing T43, the memory field storing data in the first memory circuit 101 designated by the row address and the column address enters a data read state when the column address A2HCAADDR and the CAS signal A1LCCAS are inputted to the first memory 101. The data N1INDATA stored in the memory field is then read and outputted to the data bus when the control signal A1HCDDE of the H level is inputted to the first memory 101.
After the memory test operation for the first memory circuit 101 is completed, the memory test operation for the second memory circuit 102 will be executed. At the timing T52 shown in FIG. 3, the second memory circuit 102 enters the active state when receiving the row address A  less than   greater than  and the control signal /RAS.
Following this operation, at the timing T53 shown in FIG. 3, the column address A  less than   greater than  and the /CAS signal are supplied to the second memory circuit 102. Then, at the timing when the control signal OE is inputted, the data stored in the memory field in the second memory circuit 102 indicated by the row address and the column address is read and outputted to the data bus (not shown).
Because the conventional semiconductor processing device incorporating two kinds of the memory circuits 101 and 102, whose operation timings are different and operate based on different access methods, has the configuration described above, it must be required to execute the memory test operation for each of the memory circuits 101 and 102, independently. Accordingly, it is required to prepare test patterns for each kind of the memory circuits 101 and 102. This configuration of the conventional semiconductor processing device introduces several drawbacks that test patterns becomes complicated, a test period becomes long, and the cost of the memory test operation is increased.
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a memory test circuit, incorporated in a semiconductor processing device, capable of efficiently and easily executing a memory test operation even if a semiconductor processing device incorporating different kinds of memory circuits whose operation timings and accessing methods are different.
In accordance with a preferred embodiment of the present invention, a memory test circuit incorporated in a semiconductor processing device, comprises a plurality of memory means whose operation timings and accessing methods are different and control means. The control means controls test operation for the plurality of memory means. The control means recognizes the plurality of memory means as one continuous memory means based on control signal supplied from an external device, and selects one of the plurality of memory means based on the received control signals and transfers the control signals and data to be written to the selected memory means, and then reads data from the selected memory means, and transfers the read data to the external device, and then selects a following memory means in the plurality of memory means and performs the above test operation, and wherein the control means performs the test operation for all of the plurality of memory means in order continuously based on the received control signals and data.
In the memory test circuit as another preferred embodiment of the present invention, the control means is incorporated per the memory means, and the control means inputs an address for addressing a memory field in the memory means and an access command for designating access methods as the control signals and the control means decodes the address and the access command, and then selects one of the plurality of memory means based on a predetermined bit in the address, and outputs the address, the access command, the data to the selected memory means, and reads data from the selected memory means based on the address and the access command, and transfers the data read to the external device. In addition, after the test operation of the selected memory means is completed, the control means selects following memory means in the plurality of memory means in order to execute the test operation based on a predetermined bit in a following received address, and continuously executes the test operation for all of the plurality of memory means.
In the memory test circuit as another preferred embodiment of the present invention, the control means is incorporated per the memory means, and the control means inputs an address for addressing a memory field in the memory means, an access command for designating access methods as the control signals, and a control command for selecting one of the plurality of memory means. The control means decodes the address, the access command, and the control command, and then selects one of the plurality of memory means based on the control command, and outputs the address, the access command, the data to the selected memory means, and reads data from the selected memory means based on the address and the access command, and transfers the data read to the external device. After the test operation of the selected memory means is completed, the control means selects following memory means in the plurality of memory means in order to execute the test operation based on a following received control command, and continuously executes the test operation for all of the plurality of memory means.
The memory test circuit as another preferred embodiment of the present invention, further comprises a comparison means for comparing data read from the plurality of memory means. In the memory test circuit, the control means is incorporated per memory means, and the control means inputs addresses for addressing memory fields in the plurality of memory means, and access commands for designating access methods as the control signals, the control means decodes the addresses and the access commands, and outputs the addresses, the access commands, and the data to the plurality of memory means, and reads data from the plurality of memory means based on the addresses and the access commands, and transfers the data to the comparison means, simultaneously. The comparison means compares the data read from the plurality of memory means in order to check whether or not operations of the plurality of memory means are correct.